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Theory of technology that must be learned by chip manufacturers (4-1) clock technology and reset Technology

2022-06-23 18:03:12New core design

One 、 Clock technology

--GATING: A switch that controls the clock ( Logic gates are prone to burrs , Recommend special  Gating Standard Cell)
--MUX   : Control clock switching ( Logic gates are prone to burrs , Recommend special  MUX)
--DIV   : Control the frequency division of the clock 
 
-- Crystal oscillator  -> PLL -> MUX -> GATING -> DIV -> CLOCK
 
-- Clock definition 
---- Mainly check the clock path  DFF  Of  Timing  Whether the requirements for establishment time and holding time are met 
 
-- Clock purpose 
---- Provide parameters for tool timing analysis 
---- Provide a starting point for tool timing analysis (create clock/create_generate_clock)
---- Specify the relationship between clocks 
 
--DFT  Basic concepts 
----DFT  It is divided into ordinary tests ( The global clock is switched to  test_clk  To test ) And real speed test 
( On the basis of ordinary tests , stay  capture  The phase clock switches to  function  Mode to test )
---- The clock without real speed test requirements passes  clk_mux  Realization  DFT  Clock switching 
---- The clock with real speed test requirements passes  occ_clk_mux  Make a difference  DFT  Mode clock switching 
-- Be careful 
---- All clocks that require real speed testing must pass  occ_clk_mux  Handle , And there can only be one on the clock path  occ_clk_mux, You can't take any  clk_mux
-- Be careful 
----DIV/MUX  Must be on  occ_clk_mux  Before 
---- The clock is generated by  ccmu  Unified treatment 
---- Usually , Of each module  occ  from  ccmu  Modules  occ_clk_mux, If there is an additional clock source inside the module 
---- You need to instantiate one inside the module  occ_clk_mux,ccmu  The clock sent to the module does not go through  ccmu  Internal to the module  occ_clk_mux
---- Remember that the definition point of the clock cannot be selected at  clk_mux  perhaps  occ_clk_mux  The output of the , Otherwise, it will lead to  D
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