当前位置：网站首页>Ad7606 / ad7616 make zynq more powerful in the field of energy and power, and can realize 16 / 32 / 64 channel ad synchronous sampling
Ad7606 / ad7616 make zynq more powerful in the field of energy and power, and can realize 16 / 32 / 64 channel ad synchronous sampling
2022-05-14 13:57:48【Tronlong Chuang long】
1 AD7606/AD7616 Introduce
AD7606 yes ADI The company's 16 position 、8 Channel synchronous sampling AD chip , The parallel sampling rate is up to 200KSPS（AD7616 yes 16 position 、16 passageway 、1MSPS）. In power line measurement and protection system , It is necessary to synchronously sample a large number of current and voltage channels of multiphase transmission and distribution network ,AD7606 It is the most commonly used in power system at present ADC One of the sampling chips .
AD7606 On chip integrated analog input clamping protection 、 Second order anti aliasing filter 、 Track and hold amplifier 、16 Potential charge redistribution successive approximation type ADC kernel 、 Digital filter 、2.5V Reference voltage source and buffer 、 High speed serial and parallel interfaces .AD7606 use 5V Single power supply , No more positive and negative power supplies , And support ±10V or ±5V Bipolar signal input . All channels can operate at up to 200KSPS Sample at a rate of , At the same time, the input clamp protection circuit can withstand up to ±16.5V The voltage of .
at present AD7606 It has been widely used in power line detection and protection system 、 Multiple motor control 、 Instrumentation and control systems 、 Multi axis positioning system nuclear data acquisition system （DAS）.
2 ZYNQ SoC Advantages of the scheme in the field of energy and power
(1) use Xilinx Zynq-7000 SoC High performance low power processor , Integrate PS Terminal mononuclear / Dual core ARM Cortex-A9 + PL End Artix-7 Architecture programmable logic resources .
(2) It can be done by PL End Artix-7 Architecture programmable logic resources expand external functional interfaces as needed , As long as the resources meet , Theoretically, there is no quantitative limit . Typical applications ：CAN(4 road )、 Gigabit Ethernet (2 road )、 100M Ethernet (4 road )、UART(12 road )、SPI(5 road ), In particular, multiple pieces can be connected externally AD chip (AD7606/AD7616), Realization 16/32/64 road AD Synchronous sampling .
(3) OpenAMP The framework can realize dual core ARM Cortex-A9 Asymmetric usage scheme , So that the dual core ARM Realize running two systems separately ： One ARM Cortex-A9 run Linux, One ARM Cortex-A9 As a real-time kernel RTOS（FreeRTOS） Or bare metal . Real time kernel and FPGA High speed data exchange and real-time communication control with low delay , So as to meet the requirements of real-time tasks with low delay . And run Linux Of ARM Nuclear as a higher-level application , Handle more complex business transactions .
(4) Externally scalable LCD Display and touch screen control , Resolution support 2048*2048, Support 1080P HD video playback and HDMI Video output , Meet the functional requirements of various screens and human-computer interaction ;
3 AD7606 stay ZYNQ Application of the platform
Chuang long technology is Zynq-7000、OMAP-L138/C6748/F2837x + Spartan-6 And other platforms provide AD7606 The development case of .
Chuang long technology is based on Zynq-7010/7020 Industrial evaluation board for processor design TLZ7x-EasyEVM-S, It consists of a core board + Bottom plate composition . When users use the core board for secondary development , Just focus on the top application , Reduced development difficulty and time cost , It can quickly carry out product scheme evaluation and technology pre research .
chart 5 TLZ7x-EasyEVM-S Evaluation board （ Stamp hole ）
chart 6 TLZ7x-EasyEVM Evaluation board
This article takes Zynq-7000 Industrial evaluation board TLZ7x-EasyEVM-S For example , Explain ad7606_fft routine .
3.1 Functional specifications
PL End acquisition AD7606 Of 8 passageway AD The signal , The sampling rate is 200KSPS, And pass DMA IP The core caches the data to PS End DDR in （ Each channel is sampled 4096 A little bit ）, Re pass FFT IP The data will be verified FFT operation , And then FFT The results are saved to PS End DDR in , Finally through ILA Displays the original waveform and of the first channel FFT Operation result waveform .
remarks ： Because this case consumes a lot of logical resources , Therefore, this case does not support xc7z010, Support only xc7z020.
3.2 Case diagram
Click on BLOCK DESIGN Under the development interface "Address Editor" Options , You can see IP The address assigned by the kernel ,PS The terminal can pair through the corresponding address IP Nuclear control .
3.3 AD7606 modular
The module controls AD7606 Yes 8 passageway AD Signal press 200K Sampling rate , And pass the data through AXI4-Stream Interface to send .
Get into BLOCK DESIGN Development interface , Double click the module block diagram , You can view the specific configuration information of the module . The sampling rate is 200KSPS, The working clock of the module is 50MHz.
remarks ： modular 、IP You can scan the QR code at the end of the text to download details .
3.4 Case test
take TLP2P-PinBoard Adapter board connected to evaluation board CON8 Interface , then AD modular TL7606P Connect with the adapter board .
Enter the evaluation board file system , Perform the following command configuration PS-PL Level conversion register .
Target# devmem 0xf8000900 w 0xf
Use the downloader to load PL End program and PL The client program is the same as that in the directory .ltx file .
stay ila_1 Of Trigger Setup Click the button in the window , double-click axi_dma_0_m_axis_mm2s_tvalid Add it as a trigger signal .
take Value Change the value of to R, Set to rising edge trigger .
Right click Channel_1_data[15:0], Click on “Waveform Style -> Analog” Put the passage 1 The original signal is set to analog waveform .
Right click Channel_1_data[15:0], Click on “Radix -> Signed Decimal” Set data to signed type .
Refer to the above steps , stay ila_2 take axi_dma_1_m_axis_mm2s_tvalid Add as trigger signal , Set to rising edge trigger , take FFT IP The real part and imaginary part signals of the kernel output data are set as analog waveforms respectively , And set the data as signed type .
Use the signal generation source to TL7606P Modular 8 Two channels input signals respectively , The input signal tested in this case has a frequency of 2KHz、 The peak to peak is 3.3Vpp The sine wave of .
The case “sw\linux_system\image\” Copy all script files in the directory to the evaluation board file system . Execute the following command to enable axi_dma_0 Of S2MM passageway , Collect data to PS End DDR in .
Execute the following command to enable axi_dma_1 Of S2MM passageway （FFT Save the converted data to PS End DDR）, wait for FFT IP Nuclear work .
Execute the following command to enable axi_dma_0 Of MM2S passageway , Take the raw data from DDR Deliver to FFT IP nucleus .
Execute the following command to enable axi_dma_1 Of MM2S passageway , hold FFT The converted data is from DDR Deliver to ILA Show .
To configure axi_dma_0 Of S2MM passageway , Transfer data to DDR.
Good configuration DMA after , To configure axi gpio Output 1, Set up adc_enable by 1, Can make ADC transformation . Need to ensure DMA It has been configured , Make it possible again ADC Conversion and data transmission .
To configure axi_dma_0 Of MM2S passageway , take DDR Data passing AXI4-Stream Send to FFT IP nucleus .
ila_1 Original waveform
The input signal has a frequency of 2KHz、 The peak to peak is 3.3Vpp（ The voltage amplitude is 1.65V） The sine wave of . altogether 4096 A sampling point , Every sampling point 4 Clock cycles , namely 4096=16384/4.
The peak value of the wave is +10729, The trough value is -10794, Peak to peak =(10729 + 10794)/(2^16)x10V≈3.2841V, The sampling range is ±5V.
chart 26 Wave peak
chart 27 Trough value
Ila_2 FFT wave form
Channel_1_fft_IM_Dout It is the imaginary part ,Channel_1_fft_RE_Dout It is the real part .
FFT Transform points N=4096,AD Sampling rate Fs by 200KSPS. A point n The frequency represented Fn=(n-1)*(Fs/N)(n>=1). When n=1 when ,Fn by 0, Because the first point represents the DC component , So the frequency is 0, The amplitude is also 0, The sine wave has no DC component .
From the picture below we can see , In the 164 A cycle （ That is to say 42 A sampling point ） A signal appears at , Then the signal frequency Fn=(42-1)*(Fs/N)=41*200KHz/4096=2001.95Hz, And the original signal frequency 2KHz Almost the same .
amplitude （ Wave peak ） Calculation
The magnitude of a point An=( Radical sign ( Real component ^2 + Imaginary part ^2))* Compression factor /(N/2), Then the signal amplitude is An=( Radical sign (4448^2 + 3008^2))x4096/4096x2≈10739.23, Signal voltage amplitude =10739.23/(2^16/2)x5V≈1.64V, And the original signal voltage amplitude 1.65V Almost the same .
View raw data
Every sampling point 32bit（ Including real part and imaginary part ）, The address of the data of each channel is incremented in turn , From address 0x19000000 Start .
Target#devmem 0x19000000 // see V1 Channel raw data
Target#devmem 0x19000004 // see V2 Channel raw data
Target#devmem 0x19000008 // see V3 Channel raw data
Target#devmem 0x1900000c // see V4 Channel raw data
Target#devmem 0x19000010 // see V5 Channel raw data
Target#devmem 0x19000014 // see V6 Channel raw data
Target#devmem 0x19000018 // see V7 Channel raw data
Target#devmem 0x1900001c // see V8 Channel raw data
chart 30 see V1 Channel raw data
see FFT data
Every sampling point 32bit（ Including real part and imaginary part ）, The address of the data of each channel is incremented in turn , From address 0x19100000 Start .
Target#devmem 0x19100000 // see V1 passageway FFT data
Target#devmem 0x19100004 // see V2 passageway FFT data
Target#devmem 0x19100008 // see V3 passageway FFT data
Target#devmem 0x1910000c // see V4 passageway FFT data
Target#devmem 0x19100010 // see V5 passageway FFT data
Target#devmem 0x19100014 // see V6 passageway FFT data
Target#devmem 0x19100018 // see V7 passageway FFT data
Target#devmem 0x1910001c // see V8 passageway FFT data
chart 31 see V1 passageway FFT data
For case source code or detailed case description , Leave a message in the comment area , share .
- CET-6 六级考试必备范文10篇
- tensorflow学习6 -- 跑通UNet图像分割
- （Transfer Learning and fine tuning）迁移学习与微调
- ICDAR 2021竞赛 科学文献分析——表格识别综述部分（剩余部分是文档布局分析）
- Why can 128 KB soul duel achieve such a long plot?
- The price rise twice a year highlights the greed of the introduction of Jidian, and the global chip hopes to find another way out
- Second week project training report
- Third week project training report
- Fourth week project training report
- Arm is still brilliant, but it is already under siege
- Performance hit everyone, Foxconn and apple are still close, and Lixun precision seems to have failed to take advantage of the opportunity
- 5g fell from the altar. Compared with 4G, the available technology is limited, and the only advantage is that it is faster
- A new force in the field of HPC -- Fu force supercomputing
- Data center white paper (2022): the data center industry continues to upgrade and fully enables the digital economy
- Error reading registry by C WPF application
- Teach you how to do prototype design
- P4 learning - Basic forwarding
- The contents of the input box are displayed on the right
- Clickhouse 22.3 lts release
- Programmer flirting special ~ ~ ~ nice H5 cube creative photo album, resources free!!! A gift from a programmer to a girl is very suitable for a young lady!
- [missing scan tool] awvs, appscan download and installation (with network disk link)
- 5.3 binary tree_ Code implementation of optimized heap and Top-k problem
- 5.4 binary tree_ Code implementation of various traversal and calculation
- Record: com mysql. cj. jdbc. exceptions. CommunicationsException: Communications link failure... [effective through personal test]
- Record: 1221 - incorrect usage of Union and order by [effective through personal test]
- [force deduction] backtracking 1 - Foundation + combination
- What role does cloud computing play in building intelligence?
- Abstract - the shortest novel of 2016
- Fiddler packet capture guide 05: breaking points
- EDA technology and market analysis