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Main special function registers related to I / O of CC2530

2021-09-15 07:24:19 await

name

Function description

remarks

CLKCONCMD

Clock control command

bit7:32KHz Clock oscillator selection ,0 by 32KHz XOSC( Crystal oscillator ),1 by 32KHz RCOSC(RC Shock ) , Default 1. To change this bit , The system clock source must be selected as 16MHz RCOSC, namely bit6 by 1bit6: System clock source selection ,0 by 32MHz XOSC,1 by 16MHz RCOSC, Default 1bit5-3: Timer flag output ,000 by 32MHz,001 by 16MHz,010 by 8MHz,011 by 4MHz,100 by 2MHz,101 by 1MHz,110 by 500KHz,111 by 250KHz, Default 001bit2-0: Clock speed ,000 by 32MHz,001 by 16MHz,010 by 8MHz,011 by 4MHz,100 by 2MHz,101 by 1MHz,110 by 500KHz,111 by 250KHz, Default 001

CLKCONSTA

Read only clock control status

And CLKCONCMD Agreement , read-only

IEN2

Set port enable interrupt

bit1 Express P2 Interrupt enable ,bit2 Indicates serial port UART0 Interrupt enable bit4 Express P1 Interrupt enable

P1INP

Set pin data input / output mode

0 For pull-up or pull-down ,1 The three state ,P1_0 and P1_1 It can only be three states , Therefore, these two pins are generally only used for output

PCON

Power supply mode control

bit7-1:bit0: Power supply mode control , Default 0, Set up 1 Force the device to enter sleep command SLEEPCMD Power supply mode set in , When the device re enters the active state, all enable interrupts clear this bit

PERCFG

Some peripherals are configured

bit7:bit6: Timer 1 Of I/O Location ,0 Default ,1 For the second position bit5: Timer 3 Of I/O Location ,0 Default ,1 For the second position bit4: Timer 4 Of I/O Location ,0 Default ,1 For the second position bit3:bit2:bit1: Set up UART1 Of I/O Location ,0 Default ,1 Indicates the second setting bit0: Set up UART0 Of I/O Location ,0 Default ,1 Indicates the second setting

PICTL

I/O Port interrupt control parameters

bit7:,bit6-bit4 not used ,bit3 Express P2_0-P2_4 Interrupt trigger mode ,1 Trigger for falling edge ,0 Triggered for rising edge ,bit2 Express P1_4-P1_7 Interrupt trigger mode ,1 Trigger for falling edge ,0 Triggered for rising edge ,bit1 Express P1_0-P1_3 Interrupt trigger mode ,1 Trigger for falling edge ,0 Triggered for rising edge ,bit0 Express P0_0-P0_7 Interrupt trigger mode ,1 Trigger for falling edge ,0 Triggered for rising edge

Px

Data register , Set the data to be output or receive the input data

x Optional value is 0、1、2

Px_i

Data register , Set the data to be output or receive the input data

x Optional value is 0、1、2,i Value 0-7

PxDIR

Port communication direction :0 For input 、1 For export

x Optional value is 0、1、2

PxIEN

Set pin enable interrupt

x Optional value is 0、1、2

PxIF

Parallel interrupt flag ( Whole set of marks )

x Optional value is 0、1、2, Auto set ( No need to write code to set 1), Need to write code to clear ( Write code and set 0)

PxIFG

Parallel interrupt flag ( Bitwise mark )

x Optional value is 0、1、2, Auto set ( No need to write code to set 1), Need to write code to clear ( Write code and set 0)

PxSEL

Port function selection :0 For the ordinary I/O、1 For special external equipment

x Optional value is 0、1、2

SLEEPCMD

Sleep Command

bit7:32KHz RC Oscillator calibration ,0 To enable 、1 To disable , The premise is that the system clock source is 16MHz RC oscillator bit6-3:bit2: Retain , often 1bit1-0: Power supply mode ,00 Active or idle : Close only part CPU function , Other normal 01 Power supply mode 1: Clock available 10 Power supply mode 2: Clock available 11 Power supply mode 3: Except for very few essential functions , Others are completely disabled ( Including the clock ), Can only be awakened by an external interrupt

SLEEPSTA

Sleep mode status

bit7:bit6-5:bit4-3: Status bit , Record the reason for the last reset ,00 Power on reset and power down detection 、01 External reset 、 Watchdog timer reset 、 Clock loss reset bit2-1:bit0:32KHZ Clock signal ( Synchronize with the system clock )

ST

Sleep timer

ST0/ST1/ST2

STLOAD

Sleep timer loading status

T1CC0H

Counter T1 The upper limit of the count is eight digits higher

1Byte

T1CC0L

Counter T1 The upper limit of the count is eight digits lower

1Byte

T1CC2H

Timer 1 passageway 2 Capture / The upper eight digits of the comparison value

1Byte

T1CC2L

Timer 1 passageway 2 Capture / The lower eight digits of the comparison value

1Byte

T1CCTL2

Timer 1 passageway 2 Capture / Comparative control

bit7:0 Enter... For general capture 、1 by RF Capture , Default 0bit6: passageway 2 Interrupt mask ,0 To disable interrupt requests 、1 To enable interrupt request , Default 1bit5-3: passageway 2 Comparison mode selection , When the value of the timer is equal to T1CC2 Select the output operation when comparing values in :000 Compare set output 、001 Compare and clear output 、010 Compare switching output 、011 Compare the setup output up ( When the timer value is 0 Clear output when )、100 Compare the clear output up ( When the timer value is 0 Set output when )bit2: Select timer 1 passageway 2 Compare or capture patterns ,0 For capture mode 、1 For comparison mode bit1-0:

TxCTL

TxCTL It's timing / The counter Tx Register of related parameters ,[3:2] Indicates the frequency division setting ,[1:0] Indicates the counting mode

x Optional value is 1、2、3、4

T1STAT

Timer 1 state

bit7-6:bit5: Timer 1 Count overflow interrupt flag , Set when the counter reaches the final count value in free running mode bit4: Timer 1 passageway 4 Interrupt flag bit3: Timer 1 passageway 3 Interrupt flag bit2: Timer 1 passageway 2 Interrupt flag bit1: Timer 1 passageway 1 Interrupt flag bit0: Timer 0 passageway 4 Interrupt flag

U0BAUD

Set baud rate ( Transmission rate )

set baud rate

U0BUF

Data buffer register

Temporarily store data to be sent or received

U0CSR

Register for setting control and status

bit7:USART Pattern ,0 by SPI Pattern ,1 by UART Pattern bit6:UART Receiver enable ,0 To disable ,1 To enable bit5:SPI Master slave mode selection ,0 by SPI Main mode ,1 by SPI Slave mode bit4:UART Data frame error status ,0 No data frame error ,1 Bad stop bit received for byte bit3:UART check ,0 For no parity error detection ,1 Received parity error bit2: Receive byte status , read U0DBUF Automatically clear after ( Auto set 0)bit1: Transfer byte status :0 For bytes not transferred ,1 Transfer complete for bytes bit0:USART state ,0 by USART Free ,1 by USART Be busy

U0GCR

General control register

bit7:SPI The polarity of the clock ,0 Negative clock polarity 、1 Positive clock polarity bit6:SPI Clock phase ,0 Serve as SCK from 0 To 1 Output data to MOSI, And when the SCK from 1 To 0 when MISO data input ,1 Serve as SCK from 1 To 0 Output data to MOSI, And when the SCK from 0 To 1 when MISO data input bit5: The transmission is sequential ,0 by LSB Send first ,1 by MSB Send first bit4-0: Baud rate index , Set master SCK clock frequency

U0UCR

Register for setting control parameters

bit7: Clear the unit , When set to 1 when , The current event immediately stops and returns to the unit idle state bit6:UART Hardware stream enable , use RTS and CTS Use of pin selection hardware flow control ,0 Ban 、1 Can make bit5:UART Parity check ,0 Odd check 、1 Even check bit4:UART 9 Bit data enable ,0 by 8 Bit transfer ,1 by 9 Bit transfer bit3:UART Parity enable ,0 Disable parity ,1 Parity enable bit2:UART The number of stop bits ,0 by 1 Bit stop bit ,1 by 2 Bit stop bit bit1:UART The level of the stop bit ,0 Is the stop bit low level ,1 Is the stop bit high level bit0:UART The level of the start bit ,0 Is the stop bit low level ,1 Is the stop bit high level , The start bit and stop bit cannot be consistent

WDCTL

The watchdog controls

bit7-4: When the watchdog is enabled , Set to 0xA, Set it to 0x5, Timer restore , Feed the dog bit3-2: Mode setting ,11 For timer mode ( Timer T2 It's an ordinary timer ),10 For watchdog mode ,01 and 00 by IDLE Stop timer ( Once the watchdog mode is enabled, it cannot stop , But it can stop in timer mode )

This article altogether 1554 Number of words , Average reading time ≈ 4 minute

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