async fifo Of full and empty The judgment of the :

1)binary Base number ,MSB Phase at the same time ,LSB Also the same ,empty;

MSB Different time ,LSB identical ,full

2)gray code,MSB Phase at the same time ,LSB Also the same ,empty;

MSB Different ,MSB-1 Also different , The remaining LSB identical ,full;

ASYNC FIFO Medium empty and full Control flow of ,

First ptr,    ptr_w--------binary++---------gray code-------FF(wclk)--------SYNC FF(rclk)-------ptr_r

then empty

fifo The depth of the problem :

fifo It is mainly used for data caching between asynchronous clock domains .

First of all, we should understand clearly , The FIFO Application scenarios of , This is directly related to the amount of data that needs to be cached ,FIFO The depth of the .

secondly , In the process of data caching , Better not happen fifo, Full and waiting , So from a bandwidth perspective , Generally, the write bandwidth is greater than the read bandwidth ,

But in this case , If the write operation is continuous , No matter how big FIFO It doesn't make sense , therefore FIFO Write operations are generally based on Burst Of ,

In this case of discontinuous writing , adopt FIFO, To minimize , The transition from large bandwidth to small bandwidth .

therefore FIFO The depth of this is only related to , The biggest difference between the two bandwidths .

BW = Freq * Data_width

General scenarios : Free ------Burst transmission ------ Free ------Burst transmission

Extreme scenes : Free -------Burst transmission -------Burst transmission ------ Free ( Back to back transmission )

General scene :T(Burst)*BW(read)+FIFO depth >= T(Burst)*BW(write)

And keep free time ,slave You can put FIFO Reading empty .(T( Free )*BW(read) >= FIFO depth)

Extreme scenes :T(Burst)*BW(read)+FIFO depth >= 2*T(Burst)*BW(write)

And keep free time ,slave You can put FIFO Reading empty .(T( Free )*BW(read) >= FIFO depth)

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