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FSMC peripheral of stm32

2021-01-23 19:03:47 Fireflycjd

01、FSMC characteristic

Flexible static memory controller(FSMC) Flexible static storage controller .FSMC Can be connected to asynchronous or synchronous memory or 16 position PC Memory card , The main uses are :

  • take AHB Data communication transactions are translated into appropriate external device protocols

  • Meet the access timing requirements of external devices

All external memories share addresses 、 Data and control signals , But it has its own selection signal .FSMC Only one external device can be accessed at a time .

FSMC, Flexible static storage controller , Ability to work with synchronous or asynchronous storage and 16 position PC Memory card connection ,STM32 Of FSMC Interface support includes SRAM、NANDFLASH、NORFLASH and PSRAM Equal storage .

△FSMC Schematic diagram

 

02、AHB Interface

AHB The device interface enables the internal CPU And other main bus peripherals to access external memory .AHB Transactions can transfer external device protocols . Especially when the external memory is selected bit 8 Bit or 16 position ,32 Bit AHB Transport transactions are divided into multiple consecutive 8 Bit or 16 Transport transactions for . The selection will switch every time you visit .

General transaction rules require AHB The transmission data width must be 8 position 、16 Bit or 32 position . But access to external data must have a fixed data width . This can lead to different transmissions .

So you have to follow some simple transaction rules :

  • AHB The transaction data width must be the same as the memory data width . There is no problem in this case ;

  • AHB Transaction data width is greater than memory data width , under these circumstances ,FSMC Will AHB Transactions are divided into multiple consecutive memory accesses , This corresponds to the external memory access data width ;

  • AHB Transaction data small memory width , under these circumstances , Asynchronous transmission may be consistent , It can also be inconsistent , It depends on the type of external device .

Asynchronous access to the device should have byte selection function (SRAM,ROM,PSRAM),①FSMC Allow write transactions to select channels through their bytes NBL[1:0] Access the right data ,② Allow read transactions . Will read all memory bytes , And will discard useless memory bytes . NBL[1:0] Remains low during read transactions .

For devices without byte selection function ( 16 position NOR and NAND Flash) Asynchronous access , When the request is right 16 The seat is wide Flash This happens when the memory is accessed by bytes .

obviously , This device cannot be accessed in byte mode ( Only for Flash Memory read or write 16 Bit words ), therefore ① Write transactions are not allowed ,② Allow read transactions . Will read all memory bytes , And will discard useless memory bytes . NBL[1:0] Keep low during read transactions .

 

03、 External device address mapping

FSMC External device address image of ,STM32 Of FSMC Divide external memory into fixed sizes of 256M Four memory blocks of bytes :

  • block 1 Be used for 4 individual NORflash perhaps PSRAM Memory devices . block 1 Is divided into 4 block NORflash/PSRAM With independent chip selection signal .

  • block 2 And block 3 Used to connect to NANDflash( A block drives a device )

  • block 4 Used to connect to PC Block device

For each storage area , The type of memory to be used is defined by the user in the configuration register

 

NOR/PSRAM Address mapping

Bank1 Of 256M Byte space is made up of 28 Root address line (HADDR[27:0]) Addressing . here HADDR, It's internal AHB Address bus , But it's also involved in addressing external memory , among ,HADDR[25:0] From external memory address FSMC_A[25:0], and HADDR[26:27] Yes 4 The address of each area . As shown in the following table :

HADDR[25:0] Contains the external memory address . because HADDR For byte address , And memory is addressed word by word , So depending on the width of the memory data , The address actually sent to memory will also be different , As shown in the following table :

When Bank1 The next thing is 16 Bit width memory :HADDR[25:1]->FSMC_A[24:0];

When Bank1 The next thing is 8 Bit width memory :HADDR[25:0]->FSMC_A[25:0];

Regardless of the external connection 8 position /16 Bit width devices ,FSMC_A[0] Always connect to the external device address A[0].

 

04、NOR/PSRAM controller

FSMC Will generate the appropriate signal timing , To drive the following types of memory

  • asynchronous SRAM and ROM,8 position 、16 Bits or 32 position

  • PSRAM, Asynchronous mode , Burst mode , Reuse or non reuse

  • NOR Flash, Asynchronous mode or burst mode , Reuse or non reuse

FSMC Each block outputs an independent chip selection signal NE[4:1]. Other signals ( read , Data and control ) Is Shared ;

For synchronous access ,FSMC Clock the selected external device only when reading and writing transactions .HCLK The clock frequency is an integral multiple of the clock . The size of each block is fixed 64M byte .

The programmable parameters of memory include access timing ( As shown in the figure below ) And support for waiting management ( For accessing in burst mode NOR Flash and PSRAM).

NOR/PSRAM Programmable access parameters for

 

05、 External memory interface signal

Non multiplexing I/OPSRAM/SRAM

Be careful : Prefix “N” Indicates that the associated signal is low level active

 

06、NOR/PSRAM Controller asynchronous transactions

Asynchronous static memory (NOR Flash、PSRAM、SRAM)

  • The signal passes through the internal clock HCLK To synchronize , This clock will not be sent to memory ;

  • FSMC Always sample the data first , And then disable the chip select signal NE. This ensures that the memory data holding timing requirements are met ( Data conversion chip enables high level , Usually the lowest is 0 ns.);

  • If you enable extended mode (FSMC_BCRx In register EXTMOD Location 1), You can provide up to four extension modes ( A、 B、 C and D). It can be mixed A、 B、 C and D Mode to read and write . for example , It can be in mode A To perform a read operation under , And in mode B Write operations are performed under ;

  • If extended mode is disabled (FSMC_BCRx In register EXTMOD Bit reset ), be FSMC It can be in mode 1 Or mode 2 Run under , As follows ① When choosing SRAM/CRAM Memory type , Pattern 1 Default mode ( FSMC_BCRx In the register MTYP = 0x0 or 0x01)② When choosing NOR Memory type , Pattern 2 Default mode ( FSMC_BCRx In the register MTYP =0x10)

For this 5 Patterns , Summarized below :

Pattern 1/A:SRAM/PSRAM(CRAM)OE Flip , Pattern A With the model 1 Is the difference between the NOE And independent reading and writing timing .

Pattern 2/B:NOR Flash memory , Pattern 2/B With the model 1 Comparison , The difference is NADV The change of , And in extended mode ( Pattern B) Read and write sequences are independent of each other .( Only when extended mode is set ( Pattern B),FSMC_BWTRx It works , Otherwise, the contents of the register will not work .)

Pattern C :NOR Flash memory - OE Flip , Pattern C With the model 1 The difference is ,NOE and NADV The flip change of , And independent read and write timing ;

Pattern D: Asynchronous operation with address extension , Pattern D With the model 1 The difference is NADV The flip change of ,NOE The flipping of is in NADV After flipping , And it has independent reading and writing timing .

 

07、 Pattern 1

Pattern 1 -SRAM/PSRAM (CRAM)

The figure below shows the read and write transactions that follow the supported mode through configuration FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx register

▽ Pattern 1 Read access

▽ Pattern 1 Write an interview

At the end of a write transaction HCLK The cycle helps to ensure that NWE Address and data holding time after rising edge . Because of this HCLK cycle ,DATAST The value must be greater than zero (DATAST > 0).

 

08、 Pattern A

Pattern A -SRAM/PSRAM (CRAM) OE Switch

▽ Pattern A Read access

▽ Pattern A Write an interview

With the model 1 The difference is that NOE Switch with independent read and write timing

 

For mode A,

ADDSET Namely NWE High level time , That's when the address was set up

DATAST Namely NWE Low level time , That is, data retention time

 

09、 Code instructions

readWriteTiming.FSMC_AddressSetupTime = 0x02;   // Address establishment time (ADDSET) by 2 individual HCLK 2*1/120M=16ns
readWriteTiming.FSMC_AddressHoldTime = 0x02;   // Address hold time (ADDHLD),16ns  
readWriteTiming.FSMC_DataSetupTime = 0x06;     // Data establishment time ,50ns
readWriteTiming.FSMC_BusTurnAroundDuration = 0x00;// Bus recovery time 
readWriteTiming.FSMC_CLKDivision = 0x00;//  Clock division factor  
readWriteTiming.FSMC_DataLatency = 0x00;// Data generation time 
readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;   // Pattern A

FSMC_AddressSetupTime: These bits define the establishment time of the address , Apply to SRAM、ROM And asynchronous bus multiplexing mode NOR Flash operation .

FSMC_AddressHoldTime : These bits define the retention time of the address , Apply to SRAM、ROM And asynchronous bus multiplexing mode NOR Flash operation .

FSMC_DataSetupTime: These bits define the holding time of the data , Apply to SRAM、ROM And asynchronous bus multiplexing mode NOR Flash operation .

FSMC_BusTurnAroundDuration: These bits are used to define the delay on the bus after a read operation ( For bus reuse mode only NOR Flash operation ), After a read operation, the controller needs to send the address for the next operation on the data bus , This delay is to prevent bus conflicts . If the extended memory system does not contain memory in bus multiplexing mode , Or the slowest memory can be in 6 individual HCLK Return the data bus to the high resistance state in the clock cycle , You can set this parameter to its minimum value .

FSMC_CLKDivision : Definition CLK The period of the clock output signal , With HCLK The number of cycles represents .

FSMC_DataLatency: In synchronous group mode NOR Flash memory , You need to define the number of memory cycles to wait before reading the first data . This time parameter is not based on HCLK Express , It's a flash clock (CLK) Express . When accessing asynchronous NOR Flash memory 、SRAM or ROM when , This parameter doesn't work . operation CRAM when , This parameter must be 0

FSMC_AccessMode : Access pattern

FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;//   Here we use NE1 , It corresponds to BTCR[6],[7].
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;//  Do not reuse data address 
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;// FSMC_MemoryType_SRAM; 
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;// The memory data width is 8bit   
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;//   Memory write enable 
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;//  Read and write using the same timing 
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &readWriteTiming;// Read write timing 
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &readWriteTiming;// Write timing 

FSMC_Bank:nor It's divided into four , This parameter is used to program that block

FSMC_DataAddressMux: Address \ Whether the data is reused

FSMC_MemoryType: Memory type

FSMC_MemoryDataWidth: Data bus width 8 position /16 position  

FSMC_BurstAccessMode: Group mode access or not

FSMC_WaitSignalPolarity: Wait for the signal validity level

FSMC_WrapMode: This bit determines whether the controller supports the misaligned AHB Group operations are divided into 2 Sublinear operations ; This bit is only valid in group mode of memory .

FSMC_WaitSignalActive: When flash memory is in group transfer mode ,NWAIT The signal indicates whether the data coming out of the flash memory is valid or whether the waiting period needs to be inserted . This bit determines that the memory is generated one clock cycle before the waiting state NWAIT The signal , Or during the waiting state NWAIT The signal .

FSMC_WriteOperation: This bit indicates FSMC Whether to allow / Write operations to memory are prohibited .

FSMC_WaitSignal: When flash memory is in group transfer mode , This one allows / No Admittance NWAIT Signal insertion waiting state .

FSMC_ExtendedMode: This bit allows FSMC Use FSMC_BWTR register , That is to allow different timing for reading and writing .

FSMC_WriteBurst: For flash memory in group transfer mode , This one allows / No Admittance NWAIT Signal insertion waiting state . The synchronous group transfer protocol enable bit for read operation is FSMC_BCRx The register of BURSTEN position .

FSMC_ReadWriteTimingStruct: Read timing configuration pointer

FSMC_WriteTimingStruct: Write timing configuration pointer

 

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