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A former arm engineer's criticism of risc-v

2020-12-07 15:21:32 InfoQ

{"type":"doc","content":[{"type":"blockquote","content":[{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" This paper was first completed a few years ago , At that time the author was ARM The company holds the position of executive core verification engineer ."},{"type":"text","marks":[{"type":"strong"}],"text":" The author's work at that time went deep into or around a variety of processor cores , And the ideas mentioned in the article are deeply influenced by these experiences , let me put it another way , These views are biased to varying degrees "},{"type":"text","text":"."}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" The author still insists that RISC-V The design is not perfect , But it also admitted that , If you need to build one now 32 or 64 Bit CPU, He will also benefit from existing tools as he implements the build ."}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" This paper is mainly based on RISC-V ISA standard v2.0, Section has been updated to v2.2."}]}]},{"type":"heading","attrs":{"align":null,"level":2},"content":[{"type":"text","text":" Preface to the original text : Some viewpoints "}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"RISC-V ISA The pursuit of minimalism is at its best , It strongly emphasizes reducing the number of instructions , Standard coding and so on . This pursuit leads to the wrong orthogonality ( Branch 、 call 、 Repeat the same instruction on return ), And the need for redundant instructions , These affect code density in terms of program size and number of instructions ."}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" With the following C Code, for example :"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"int readidx(int *p, size_t idx){ return p[idx]; }\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" Simple array index , Very common operations . Put it in x86_64 Chinese compiler :"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"mov eax, [rdi+rsi*4]ret\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" Or is it ARM in :"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"ldr r0, [r0, r1, lsl #2]bx lr \/\/ return\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":" But in RISC-V The code needed in is :"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"# I'm sorry if there are any grammatical errors ,risc-v There is no online compiler slli a1, a1, 2add a0, a1, a1lw a0, a0, 0jalr r0, r1, 0 \/\/ return\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"RISC-V Let the decoder (CPU front end ) Make it easier , The cost is that more instructions need to be executed . However , Compared with the problem of broadening the assembly line , The problem of decoding irregular instructions is easy to solve , The main difficulty is to determine whether the length of instructions is consistent .x86 A lot of prefixes are an excellent example of the opposite . The simplification of instruction set should not pursue the limit . register + The memory operation instruction of shift register is a very common and simple operation in program , about CPU It's also easy to implement . Even if it can't be executed directly ,CPU It can also be executed relatively easily in steps , The complexity of its operation is much less than the sequence of simple operations ."}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}}]}

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