# Implementation of modular multiplication in GF (2 ^ 8) finite field with Verilog combinatorial logic

2020-12-01 12:06:52

``````wire [7:0] x, y;
wire [7:0] z;
assign z = {

x[7]&y[0] ^ x[6]&y[1] ^ x[5]&y[2] ^ x[4]&y[3] ^ (x[7]^x[3])&y[4] ^ (x[7]^x[6]^x[2])&y[5] ^ (x[6]^x[5]^x[1])&y[6] ^ (x[7]^x[5]^x[4]^x[0])&y[7],

x[6]&y[0] ^ x[5]&y[1] ^ x[4]&y[2] ^ (x[1]^x[3])&y[3] ^ (x[7] ^ x[6]^ x[2])&y[4] ^ (x[6]^x[4]^x[1])&y[5] ^ (x[7]^x[5]^x[4]^x[0])&y[6] ^ (x[3]^x[4]^x[6])&y[7],

x[5]&y[0] ^ x[4]&y[1] ^ (x[7]^x[3])&y[2] ^ (x[7]^x[6]^x[2])&y[3] ^ (x[6]^x[4]^x[1])&y[4] ^ (x[7]^x[5]^x[4]^x[0])&y[5] ^ (x[6]^x[4]^x[3])&y[6] ^ (x[7]^x[4]^x[2]^x[1])&y[7],

x[4]&y[0] ^ (x[7]^x[3])&y[1] ^ (x[7]^x[6]^x[2])&y[2] ^ (x[6]^x[4]^x[1])&y[3] ^ (x[7]^x[5]^x[4]^x[0])&y[4] ^ (x[6]^x[4]^x[3])&y[5] ^ (x[5]^x[3]^x[2])&y[6] ^ (x[7]^x[4]^x[2]^x[1])&y[7],

x[3]&y[0] ^ (x[7]^x[2])&y[1] ^ (x[6]^x[1])&y[2] ^ (x[7]^x[5]^x[0])&y[3] ^ (x[7]^x[6]^x[4])&y[4] ^ (x[7]^x[6]^x[5]^x[3])&y[5] ^ (x[7]^x[6]^x[5]^x[4]^x[2])&y[6] ^ (x[7]^x[6]^x[5]^x[4]^x[3]^x[1])&y[7],

x[2]&y[0] ^ x[1]&y[1] ^ (x[7]^x[0])&y[2] ^ (x[7]^x[6])&y[3] ^ (x[6]^x[5])&y[4] ^ (x[5]^x[4])&y[5] ^ (x[7]^x[4]^x[3])&y[6] ^ (x[6]^x[3]^x[2])&y[7],

x[1]&y[0] ^ (x[7]^x[0])&y[1] ^ (x[7]^x[6])&y[2] ^ (x[6]^x[5])&y[3] ^ (x[5]^x[4])&y[4] ^ (x[7]^x[4]^x[3])&y[5] ^ (x[6]^x[3]^x[2])&y[6] ^ (x[7]^x[5]^x[2]^x[1])&y[7],

x[0]&y[0] ^ x[7]&y[1] ^ x[6]&y[2] ^ x[5]&y[3] ^ x[4]&y[4] ^ (x[7]^x[3])&y[5] ^ (x[7]^x[6]^x[2])&y[6] ^ (x[6]^x[5]^x[1])&y[7]

};
``````

https://chowdera.com/2020/12/20201201120631607h.html