Design of NAND flash interface control

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Nand flash yes flash One kind of memory ,Nand flash It adopts nonlinear macro cell mode and provides a cheap and effective solution for the implementation of solid state large capacity memory .NAND FLASH Memory has the advantages of large capacity and fast rewriting speed, which is suitable for the storage of large amounts of data , Therefore, it has been widely used in the industry .NAND The structure can provide extremely high cell density , High storage density , And the speed of writing and erasing is very fast . This article introduces the memory chip supplier Yuxin electronics about NAND Flash Storage structure of and NAND Flash Interface control design of .
 
NAND Flash Storage structure of
 
Most of the NAND Flash It's all the same , The only difference is that NAND Flash The basic characteristics of the chip, such as capacity size and read-write speed .
 
block Block yes NAND Flash The basic of erase operation of / Smallest unit . Page is the basic unit of read and write operations .
 
Every page , There's another area , It's called the free zone / Redundant areas , And in the Linux In the system ﹐ Generally called OOB(Out Of Band)[2]. This area was originally based on NAND Flash Hardware features of ﹐ Data is relatively error prone when reading and writing ﹐ So in order to ensure the correctness of the data , There must be a corresponding detection and error correction mechanism , This mechanism is called EDC /ECC. So the extra areas are designed ﹐ Check value used to place data .OOB Read and write operations are generally completed along with page operations , When reading and writing a page , Read and write accordingly OOB.OOB Main purpose of : Whether the mark is a bad block ﹐ Storage ECC data ﹐ Store some file system related data .
 
NAND Flash Interface control design of
 
because NAND Flash Only 8 individual I/O Pin , And it's reusable , It can transmit data ﹐ You can also send an address 、 command . Design command latch enable (Command Latch Enable,CLE) And address latch enable ( Ad-dress Latch Enable,ALE), That is to send a CLE( or ALE) command , tell NAND Flash A sound from the controller , The picture to be passed on below 1NAND Flash The control circuit is a command ( Or address ). such NAND Flash Internal ability according to the content of the incoming ﹐ Do the corresponding action . Relative to parallel port NOR Flash Of 48 or 52 One pin , Greatly reduces the number of pins , In this way, the chip is small in size . At the same time, the chip interface is reduced ﹐ The peripheral circuits associated with this chip will be simplified , Avoid cumbersome hardware wiring .